A cloud-accessible IBM processor suppresses logical memory errors

An October 16 preprint reports surface-code memory experiments on a cloud-accessible IBM superconducting processor. Increasing one protected code dimension reduces measured errors in selected short-sequence tests.

The researchers also study longer runs, where persistent correlations weaken the apparent advantage. That makes test duration part of the result rather than an incidental detail.

This is evidence about a protected memory under specific compilation, placement and decoding choices. It does not demonstrate a long, general-purpose fault-tolerant algorithm. The work is useful for showing how hardware behavior and circuit optimization interact when an error-correction experiment moves beyond a simple headline error rate.